The Hitachi HD64180 Processor
The Hitachi HD64180 Processor has the following features:
* Z80 code compatible processor core, with instruction execution pipe-lining, and many of the
fewer machine cycles than the original Z80. Twelve new instructions were added, including on-chip
I/O instructions, and a 'byte x byte = word' multiply instruction.
* Memory Management Unit (MMU) which supports 512k bytes of memory, and 64k bytes I/O space.
The 64k address space is divided up into up to three logical areas: Common Area 0, Bank Area,
and Common Area 1. The boundaries between the areas was locatable on 4k byte boundaries, with
Common Area 0 always starting at address 0 (if it is enabled).
* Two channel Direct Memory Access Controller (DMAC) which supports memory-to-memory,
memory-to-I/O, and memory-to-memory mapped I/O transfers. The DMAC memory registers support
the full 512k byte physical memory address space, so blocks of up to 64k bytes in size can
be moved, even across 64k byte boundaries, anywhere in memory.
* Programmable wait state generator, for both memory and I/O access cycles.
* Programmable DRAM refresh address and timing.
* Two channel, full-duplex Asynchronous Serial Communication Interface (ASCI), with programmable
Baud rate generator, and modem control hand-shake signals. The SB180's 6.144MHz clock gave a Baud
rate range of 300 to 19200 baud.
* Two channel 16-bit Programmable Reload Timer (PRT).
* Programmable Interupt Controller, with four external inputs, and eight internal signals.
* Clock generator.
Here is a block diagram: